Void-Free Metallic Filled High Aspect Ratio Openings

ABSTRACT

One embodiment is a device which includes at least one filled via or trench wherein the at least one filled via or trench includes void-free filled metal or alloy, and the filled via or trench has an aspect ratio in a range from 9:1 to about 28:1.

This is a continuation of application Ser. No. 13/690,292, filed on Nov.30, 2012, which is a continuation of application Ser. No. 11/827,829,filed on Jul. 13, 2007, now U.S. Pat. No. 8,349,149, which is acontinuation of application Ser. No. 11/085,971, filed on Mar. 21, 2005,now U.S. Pat. No. 7,247,563, which is a continuation of application Ser.No. 10/112,332, filed on Mar. 29, 2002, now U.S. Pat. No. 6,869,515,which itself claims the benefit under 35 U.S.C. 119(e) of U.S.Provisional Application No. 60/280,325 filed on Mar. 30, 2001. All theabove preceding applications and patents are incorporated herein byreference in their entirety.

BACKGROUND

This invention relates to the field of metal or alloy electrochemicaldeposition (ECD) for filling narrow and high aspect ratio openings. Inparticular, the invention discloses new methods which enhance reliable,fast, and void-free filling of very small openings, with large aspectratios, such as vias and trenches in semiconductor devices, thin filmheads, electronic high density packages, or micro electromechanicalsystem (MEMS) devices. The new methods are particularly effective forthe so called “Damascene” and “Dual Damascene” copper interconnects,providing fast, reliable, and void-free copper filling by electroplatinginside vias and trenches in the manufacture of semiconductor devices.

There are two methods to fill patterned openings by electroplating. Inone method, an insulating mask such as an oxide, photoresist, orpolyimide layer is patterned over a conductive metallic surface (or a“seed layer” or “plating base”), exposing the metallic surface only atthe bottom of the openings. Electroplating is carried out through theopenings in the insulating mask, and is confined inside the openings ofthe mask. Usually, following the plating, the insulating mask is removedand the seed layer (which was covered by the insulating mask) is etchedaway. This method is often used in the fabrication of, for example,coils and other metallic structures of thin film heads, metallicconductors in high density packages, and in MEMS devices.

In the other method, sometimes referred to as “Damascene” or “DualDamascene”, an insulating (or dielectric) layer is first pattern-etchedto form openings in it. Next, at least one metallic layer is depositedover the insulating layer to metallize its top surface (field), as wellas the sidewalls and bottom surfaces of the openings. The metalliclayer(s) serves as a conductive plating base (or “seed-layer”), toprovide low resistive electric path for the electroplating current.Electroplating is then carried out over the entire metallized surface,including the field and inside the patterned openings. Followingplating, the plated metal and any metallization (adhesion, barrier, orseed) layers above the field, as well as any excess plated metal overthe openings, are removed by etching, polishing, or by chemicalmechanical polishing (CMP). This results in metallic filled vias ortrenches (or grooves), surrounded by a dielectric. This method is used,for example, to produce metallic interconnects in semiconductorintegrated circuits devices.

Usually, when using electrolytes without surface active additives, theplating rate inside the openings is slower than at the field. Due tohigher electric field at the top corners of the openings, the localcurrent density (and plating rate) is higher at the top corners, leadingto faster growth and pinching-off of the top corners. This leads todeleterious voids in the filling, as shown in FIG. 1. Also, duringelectroplating, the relatively stagnant electrolyte inside the openingsresults in poor replenishment and depletion of the plating ion there.This leads to slower plating rate inside the openings than over thefield, resulting in voids in the filling (cf. FIG. 1). The plating iondepletion is more severe at the bottom of the openings, and less severenear the top corners. The plating ion concentration gradient producesincreasing concentration polarization, which leads to a decreasingplating rate along the depth of the opening. These inherent void-formingproblems become more severe with decreasing width and increasing aspectratio of the openings. The higher the aspect ratio (AR) of the opening,the slower the plating rate inside it, relative to the field. Theseproblems result in poor or incomplete (voids) filling of high ARopenings (cf. FIG. 1).

Aspect ratio (AR) is defined herein (cf. FIG. 1) as the ratio betweenheight (or depth), h, of an opening and its smallest lateral dimension,W (width of a trench, or diameter of a via):

AR=h/W

The openings may consist of, for example, vias or trenches (or grooves)in a dielectric layer, such as used in the fabrication of interconnectsin semiconductor integrated circuit devices.

The filling problems become more severe with decreasing lateraldimension W and increasing AR of the openings. For example, in today'smost advanced copper filling of trenches and vias in integrated circuitinterconnects, the openings may have an aspect ratio as high as 8:1(h=1.4 μm; W=0.18 μm), and future trench and via openings will likelyrequire W≦0.10-0.13 μm, and AR≧10:1. Reliable, void-free filling of suchnarrow and high AR openings imposes a great deal of difficulty.

In order to overcome the natural tendency to form voids, commercialelectrolytes, such as acidic copper sulfate, usually include proprietarysurface active “brightener” and/or “leveler” additives. The proprietaryadditives usually comprise organic compounds with functional groupscontaining sulfur and/or nitrogen atoms. These compounds adsorb ontogrowth sites of the depositing metal surface, thereby inhibiting (orsuppressing) the metal deposition rate. The adsorption and itsassociated inhibition lead to smaller (finer) grains of the depositingmetal, thus producing smoother and brighter deposits. Leveling isobtained by higher concentration of inhibitor (or additives) atprotrusion tips sticking into the diffusion layer, thereby inhibiting(or suppressing) their growth. As a result, inhibition is stronger atprotrusions, compared with the flat surface. In much the same way, therelatively stagnant electrolyte inside narrow openings results in poorreplenishment and depletion of the inhibitor there. This depletionresults in reduced inhibition and faster growth inside the openings. Dueto better supply of the inhibitor at the top corners and the field,inhibition is stronger at the top corners of openings and at the field(compared with inside the openings). The reduced inhibition insidenarrow openings speeds up the plating rate there (relative to thefield), thus facilitating void-free filling (or “superfilling”) ofnarrow openings with large aspect ratios. The mechanism of superfillingnarrow openings, using inhibiting additives, was proposed in severalpublications. For examples, see an article entitled: “Damascene copperelectroplating for chip interconnects”, by P. C. Andricacos, at al. inIBM Journal of Research and Development, Vol. 42(5), pp. 567-574, 1998,and an article entitled: “Copper On-Chip Interconnections”, by P. C.Andricacos in The Electrochemical Society Interface, pp. 32-37, Spring1999.

Clearly, in order to achieve void-free “superfilling” of narrowopenings, the beneficial effect of inhibition gradients must overcomethe intrinsic void-forming effects due to (a) higher electric field (andcurrent density) at the top corners and, (b) decreasing plating rateinside openings along their depth due to depletion of the plating ionthere.

As openings get narrower, and the aspect ratio increases, void-freeECD-filling becomes harder and harder to control. While wider openingsmay fill well, narrower ones may have voids, and vice versa. Forexample, see an article entitled: “Factors Influencing Damascene FeatureFill Using Copper PVD and Electroplating”, by J. Reid et al. in Journalof Solid State Technology, Vol. 43(7), pp. 86-103, July 2000. Processlatitude, such as the useful range of additive concentration and/orplating rate, becomes very tight and hard to control.

Prior art ECD tools and methods commonly employ relatively slow laminar(or “natural”) flow of electrolyte across the substrate's surface. Forexample, U.S. Pat. Nos. 6,080,291, 6,179,983, and 6,228,232 employ aperforated (or “diffusion”) plate or a porous membrane, placed betweenthe anode and cathode (substrate), in order to achieve laminar flowacross the substrate's surface. Such flow results in a relatively thickdiffusion layer. The thick diffusion layer limits the useful platingrate to only about 0.3-0.4 μm/min, thereby limiting the throughput ofsingle-wafer plating modules. In addition, prior art Cu-plated wafersusually display relatively rough, matte or semi-matte, surfaces. Therough plated surfaces include protrusions or bumps over filled openings,as well as spikes (or “balloons”) and steps (or “humps”) at boundariesbetween the field and patterned arrays of narrow openings (cf. FIG. 5).Such spikes, humps, or bumps cause excessive erosion and dishing duringsuccessive CMP steps and must be eliminated or minimized. Other priorart ECD tools, such as the one disclosed in U.S. Pat. No. 6,176,992 byTalieh, employ brush plating. The brush rubs the substrate's surfaceduring plating. This is claimed to result in more planar plating afterfilling the openings. However, the continuous rubbing generatesparticulates due to wear of the brush or pads, or from the depositingmetal.

Also, prior art ECD tools and methods often rely on wafer rotation toimprove axial uniformity. However, unless certain strict conditions(such as no edge effects, infinite wafer's radius, infinite electrolytevolume, low plating ion concentration, and laminar flow) are satisfied,the wafer rotation creates non-uniform electrolyte flow across itssurface. While electrolyte flow is slow at the center of the wafer, its(tangential) velocity increases with the radius. That velocitydifference increases with rotation speed. As a result, the thickness ofthe diffusion layer varies as a function of the radius R (cf. 22 in FIG.2). It has a maximum at the center of the wafer and gradually decreasesalong the radius, toward the edge of the wafer. The non-uniformdiffusion layer produces severe non-uniformity of the plated layer alongthe radius of the wafer. It may also lead to deleterious voids inECD-filled openings (such as trenches or vias) at certain radii of thewafers. These problems become more severe with increasing rotation speedand wafer diameter.

SUMMARY

Embodiments of the present invention advantageously satisfy theabove-identified need in the art and provide enhanced electrochemicaldeposition (ECD) void-free filling of a metal or an alloy insideopenings in a substrate.

One embodiment is a device which includes at least one filled via ortrench wherein the at least one filled via or trench includes void-freefilled metal or alloy, and the filled via or trench has an aspect ratioin a range from 9:1 to about 28:1.

One goal of the invention is to improve void-free filling of narrowopenings by enhancing inhibition at the field and top corners duringelectroplating, while reducing inhibition inside the openings.

Another goal is to create as large as possible concentration difference(or gradient) of the inhibitor between the field and along the depth ofthe openings, by depleting the inhibitor inside the openings and byenhancing supply and concentration of inhibitor(s) at the field and topcorners of the openings.

Another goal is to improve plating throughput and process latitude.

Yet another goal is to improve plating uniformity and void-free fillingalong the radius of plated wafers.

IN THE DRAWINGS

FIG. 1 shows a schematic cross section of a high aspect ratio openingfilled by prior art ECD. The undesirable void is produced by fasterplating rate at the field and top corners than inside the opening.

FIG. 2 compares schematic (i.e., models of) diffusion layer thicknessprofiles across a wafer diameter, produced by prior art ECD tools andmethods and by the inventive methods.

FIGS. 3 a-3 h show schematic (i.e., models of) comparisons between priorart ECD plating and by the enhanced void-free filling methods andapparatus of the present invention.

FIG. 4 shows SEM photographs of two cleaved samples with void-freeCu-filled trenches, using a JECD tool at 120 mA/cm², in accordance withthe invention. One sample shows partial fill and the other showscomplete filling of the trenches.

FIG. 5 shows a typical AFM trace taken at a boundary between the fieldand a patterned trench array, over a Cu surface plated by a conventionalprior-art ECD tool.

FIG. 6 shows a schematic (not to scale) inhibition model of brighteningand/or leveling mechanism.

FIG. 7 shows a SEM photograph of lightly etched cross section ofvoid-free Cu-filled trenches by a JECD tool, in accordance with theinvention. The trenches are ˜0.05 μm wide (at their bottom), ˜1.41 μmdeep, and have aspect ratio of about 28:1.

FIG. 8 shows an anodes/jets-nozzles assembly in accordance withembodiments of the invention. Vigorous agitation is produced by highpressure jets flow.

FIG. 9 shows an anodes/jets-nozzles assembly in accordance withembodiments of the invention. Vigorous agitation is produced by highpressure jets flow and/or by mechanical means, such as wiping brushes(or pads), or by a combination of jets and wiping brushes to enhanceinhibitor supply to the field.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In general, prior art ECD tools utilize a relatively slow (“natural” or“laminar”) flow of the electrolyte across the surface of the substrate(or wafer). The slow flow results in a relatively thick stagnantdiffusion (or boundary) layer. The thickness of the diffusion layerdecreases with the velocity of the electrolyte across the surface of thesubstrate. In prior art ECD tools, used for copper filling of integratedcircuits interconnects, the diffusion layer is typically about 20-100 μmthick. Also, the prior art ECD tools and methods often rely on waferrotation to improve axial uniformity. However, unless certain strictconditions (such as no edge effects, infinite wafer's radius, infiniteelectrolyte volume, low plating ion concentration, and laminar flow) aresatisfied, the wafer rotation creates non-uniform electrolyte flowacross its surface. For example, edge effects are always present due tothe wafer holding fixture, plating ion concentration is high,electrolyte volume is small, and rotation speed of more than about 80revolutions per minute (RPM) of 300 mm wafers produces non laminar flownear the edge. As a result, prior art ECD tools and methods usuallyproduce a mix of laminar and some turbulent flows.

FIG. 2 shows schematic (not to scale i.e., models of) distributionprofiles of the diffusion layer thickness ΔX across a wafer,corresponding to prior art tools and methods 22 and the inventivemethods 24, respectively. Due to wafer rotation in the prior art ECDtools, electrolyte flow at the center of the wafer is slow, but the flow(tangential) velocity increases with the radius R. As a result, thediffusion layer thickness ΔX varies as a function of the radius (cf.22). It has a maximum at the center of the wafer and decreases along theradius, toward the edge of the wafer. The non-uniformity of thediffusion layer becomes worse with increasing rotation speed and waferdiameter. The non-uniform diffusion layer produces severe non-uniformityof the plated layer along the radius of the wafer. It may also lead todeleterious voids (cf. FIG. 1) in ECD-filled openings (such as trenchesor vias), at certain radii of the wafers. These problems become moresevere with increasing wafer rotation speed and diameter. In contrast,the inventive methods and apparatus produce substantially uniformvigorous agitation, resulting in much thinner and uniform diffusionlayer thickness across the wafer (cf. 24). Although the inventivemethods may also utilize wafer rotation (to improve axial uniformity),the rotational flow component is relatively small, compared with theother vigorous flow components.

In a preferred embodiment, uniform vigorous electrolyte agitation at thefield outside openings is produced, for example, by using high pressureJets ECD (JECD), such as disclosed in U.S. Pat. No. 5,421,987 (Jun. 6,1995), by Tzanavaras and Cohen, incorporated herein by reference. Thepowerful high pressure jets agitation can readily reduce the fielddiffusion layer thickness by an order of magnitude, to about 2-10 μm, orless, thereby significantly enhancing replenishment of the inhibitor atthe field. At the same time, the electrolyte remains essentiallystagnant inside narrow openings, thus leading to local depletion ofinhibitor there. In addition, the vigorous jets agitation also mitigatesnon-uniformity of the diffusion layer thickness along the wafer'sradius, due to wafer (or anodes/jets assembly) rotation. The powerfulturbulent jets flow is much more prevalent than the rotational flow.

EXAMPLE 1

Limiting current measurements (of plating current saturation atincreasing cathode voltage) were taken with and without jets flow, usinga jets ECD (JECD) tool similar to the one disclosed in U.S. Pat. No.5,421,987. The acidic copper electrolyte did not include any inhibitionorganic additives. It consisted of 0.3M CuSO₄, 10% (v/v) H₂SO₄, and ˜60ppm chloride ions. In one measurement, a “natural” flow of about 2gallons per minute (GPM) was used through an inlet at the bottom of theplating cell. The observed limiting current density, i_(L), was about 55mA/cm². In another measurement, a high pressure of 40 pounds per squareinch (PSI) jets flow of 2.8 GPM was used with anode/jets assembly (AJA)rotation speed of 20 RPM, under otherwise identical conditions to thefirst measurement. The distance between the jet nozzles and the waferwas about 1″. A limiting current i_(L) could not be reached even atcurrent density as high as 733 mA/cm². Further increase of the cathodevoltage merely increased (linearly) the plating current without anysigns of approaching saturation. This represents a factor of at least13× higher limiting current using the jets flow, compared with the“natural” flow. The limiting current is inversely proportional to thediffusion layer thickness:

i _(L) =KC/ΔX

where K is a constant and C is the plating ion (bulk) concentration.These measurements indicate that the diffusion layer thickness can bereduced by at least an order of magnitude using powerful high pressureturbulent jets flow, compared with that of “natural” flow; to about 2-10μm, or less.

Due to strong damping of the jets flow in the bath, ΔX and i_(L) aresensitive to the (inlet) jets pressure and to the distance between thejet nozzles and the substrate's surface. The higher the jets pressureand the closer the substrate's surface to the jet nozzles, the thinneris ΔX and the larger is i_(L). For reasons of system integrity, avoidingdevice damage by the jets, pump cost, and heat generation, a pressurerange of 30-50 PSI is preferred. The distance between the substrate'ssurface and the jet nozzles is optimized between conflictingrequirements. On one hand it is desirable to shorten this distance asmuch as possible, in order to mitigate bath damping and to achievepowerful jets impinging on the substrate. On the other hand, theoverlapping area on the substrate covered by neighboring jets is reducedwith the distance between the nozzles and the substrate. Lack ofsufficient overlap between the jet cones leads to periodicnon-uniformity across the substrate. The preferred optimized distancebetween the nozzles and the substrate is in the range of about 0.5-2.0″,and more preferably in the range of 0.75-1.5″.

FIGS. 3 a-3 h show schematic (not to scale i.e., models of) comparisonsbetween prior art ECD-filling, and the enhanced void-free ECD-filling ofthe present invention. Inhibitor additives are used in both cases.Plating inhibition (or suppression) can be produced by many surfaceactive materials (adsorbates) which adsorb onto the surface of theplating metal or alloy.

FIGS. 3( a) and 3(b) compare inhibitor concentration profiles 31, ofprior art ECD methods and/or tools, and the present invention,respectively. Concentration profiles 31 are shown as a function of thedistance X into the electrolyte, adjacent to a flat substrate surface30. The prior art diffusion layer thickness (ΔX₁) is much larger thanthat produced by the inventive methods of the present invention (ΔX₂):

ΔX₁

fsi ΔX₂

During electroplating, inhibitor is consumed at the advancing depositsurface, thereby depleting its interface concentration. The interfaceconcentration is smaller than the bulk concentration, C_(∞). Aconcentration gradient of the inhibitor is thus established across the(stagnant) diffusion layer. Due to much thinner diffusion layer of theinventive methods, the inhibitor flat (or field) interface concentration(C_(F2)) of the inventive methods is much larger than that of prior art(C_(F1)):

C_(F2)

fsi C_(F1)

FIGS. 3( c) and 3(d) compare the inhibitor concentration profiles 33inside a narrow opening 34, and at adjacent field 32 outside theopening. FIGS. 3( c) and 3(d) correspond to conventional prior art ECDmethods and/or tools, and to the inventive methods, respectively. As iswell known to those skilled in the art, multiplicity of openings, suchas opening 34, are etched in a dielectric (or insulating) material 36prior to electroplating. Although the description herein relatessometimes to a single opening 34, it should be understood by thoseskilled in the art that the same description also applies tomultiplicity of openings 34. Similarly, although the description hereinrefers to a single inhibitor, it should be understood by those skilledin the art that the same description also applies to multiplicity ofinhibitors. Opening 34 includes sidewall surfaces 37 and bottom surface38. Also as well-known, prior to electroplating, a metallic barrierlayer and a copper seed layer (not shown) are formed by dry depositiontechniques, such as by physical vapor deposition (PVD) or by chemicalvapor deposition (CVD). The metallic barrier and the Cu seed layer mustbe continuous over the surfaces of sidewalls 37 and bottom 38 ofopenings 34, as well as over the field 32. The barrier layer usuallycomprises a refractory metal (such as Ta or Ti) or an alloy comprising arefractory metal (such as TaN_(X) or TiN_(X)). The barrier layer servestwo functions: to minimize out-diffusion of Cu into the dielectricmaterial 36 and/or into the underlying semiconductor device (not shown),and to improve adhesion between dielectric material 36 and the Cu seedlayer. The Cu seed layer provides low electrical resistance path on thesurface, required for the electroplating.

FIGS. 3( c) and 3(d) show that during electroplating, due to asubstantially stagnant electrolyte inside opening 34, the inhibitor isgreatly (or fully) depleted near the bottom 38 of opening 34. Theinventive methods aim to enhance replenishment of the inhibitor at thetop field surface 32. They produce much larger inhibitor's concentrationat the field than that obtained by prior art: C_(F2)

fsi C_(F1). Inhibitor concentration variances (between the field 32 andthe opening's bottom 38) are defined herein:

ΔC ₁ =C _(F1) −C _(B1) (cf. FIG. 3(c); prior art)

ΔC ₂ =C _(F2) −C _(B2) (cf. FIG. 3(d); present invention)

Clearly, the concentration variance (or difference) obtained by theinventive methods is much larger than that obtained by prior art: ΔC₂

fsi ΔC₁. The inventive methods greatly enhance inhibition (andslowing-down) of electroplating rate at the field 32, relative to insideopening 34.

FIGS. 3( e) and 3(f) show plating rate profiles 35 obtained by prior artECD methods and tools, and by the inventive methods, respectively. Dueto essentially stagnant and small volume (and large area/volume ratio)of the electrolyte inside the opening, the plating depletes theinhibitor there. This depletion establishes concentration gradients ofthe inhibitor along the sidewalls (depth) of the opening, with maximumdepletion at the bottom 38. The degree of inhibition inside opening 34decreases gradually along its depth and has a minimum near its bottom38. This results in maximum plating rate near bottom 38, and slowerplating rate at the field 32 and top corners. Plating rate variances(between opening's bottom 38 and field 32) are defined herein:

ΔV ₁ =V _(B1) −V _(F1) (cf. FIG. 3(e); prior art)

ΔV ₂ =V _(B2) −V _(F2) (cf. FIG. 3(f); present invention)

Positive plating rate variance (ΔV>0) facilitates void-free filling (or“superfilling”) of narrow openings. The larger this variance, the morepronounced and prevalent the superfilling mechanism. While prior art ECDmethods and tools provide relatively small (or marginal) plating ratevariance, the inventive methods produce much larger variance: ΔV₂

fsi ΔV₁. In other words, prior art ECD methods and tools produce onlyslightly larger plating rate at the bottom 38 than at the field 32:V_(B1)≳V_(F1). In fact, due to inherent competing void-formingmechanisms, they often result in negative variance: ΔV₁≲0. In contrast,the inventive methods greatly enhance inhibition at the field 32 and topcorners, thereby significantly slowing-down the plating rate there(relative to bottom 38): V_(B2)

fsi V_(F2). The inventive methods aim at producing large plating ratevariance: ΔV₂

fsi 0. They thus overcome inherent void-forming mechanisms (due tohigher electric field at the top corners and due to depletion of platingions inside openings). These inherent void-forming mechanisms producenegative plating rate variance (ΔV<0), leading to pinching-off of thetop corners, and to void-formation. The inventive methods significantlyenhance void-free superfilling by generating a large and positive ΔV₂.This large variance also facilitates wider process latitude, such aswider useful ranges of inhibitor concentration and plating rates.

FIGS. 3( g) and 3(h) show filling profiles 39 obtained by prior art ECDmethods and tools, and by the inventive methods, respectively. Whileprior art methods and tools produce conformal (or marginally filling)profiles which often lead to seam-voids, the inventive methods producemuch more pronounced superfilling profile. Robust prevalent superfillingis the result of significantly slower plating rate at the field 32 andtop corners, with a pronounced maximum near bottom 38, as shown in FIG.3( f). Such a plating rate profile facilitates progressive sealing ofnarrow openings without seam-voids (“superfilling”). This sealingproceeds like a zipper, from bottom to top, where most of the filling isdue to lateral sidewall growth.

EXAMPLE 2

FIG. 4 shows scanning electron micrographs (SEM) of two cleaved sampleswith Cu-superfilled trenches, in accordance with a preferred embodimentof the invention. Both samples were plated by a jets ECD (JECD) tool,similar to the one disclosed in U.S. Pat. No. 5,421,987. Both sampleswere plated with current density of 120 mA/cm² (plating rate of about2.8 μm/min). FIG. 4( a) shows a sample in which the plating wasterminated prior to completion (partially filled trenches), therebyrevealing the superfilling profile. The growth profiles on the bottomand sidewalls in FIG. 4( a) correspond well with the superfill modelFIG. 3( h). The plating rate is fastest at the bottom (maximum depletionand minimum inhibition) and is slowest at the top (minimum depletion andmaximum inhibition) of the openings. It is the plating rate gradients,along the depth of the openings, which facilitate void-free filling ofnarrow openings. The model and the experimental results imply that, invery narrow openings (with large aspect ratios), most of the filling isdue to lateral growth components, substantially normal to the sidewalls.This explains why narrower openings fill earlier than wider openings.Almost one half of the upper width of the opening has to grow laterally,in order to seal the opening. The sealing of the opening proceedslike-a-zipper, from bottom to top. FIG. 4( b) shows a sample in whichthe plating was terminated some time after complete filling of thetrenches. Note the flat smooth Cu-plated surface and the lack of anybumps above filled openings. No plating voids were found in either ofthese samples. The jets pressure was 40 PSI, and rotation speed of theanodes/jets assembly (AJA) was 20 RPM. The distance between the waferand the nozzles was about 1″, and a backing flat plastic plate wasplaced at the back of the wafer in order to avoid wafer buckling underthe powerful jets. The acidic copper sulfate electrolyte was similar tothe one described in Example 1, and further included proprietarytwo-component (“Gleam-PPR”) additive system from Shipley-Lea RonalCompany.

The powerful jets agitation enhances replenishment of inhibitor at thefield, while inside the narrow openings the electrolyte remainsessentially stagnant. The impinging powerful jets create vigorousturbulent agitation at the wafer's surface, thereby significantlyreducing the diffusion layer thickness, ΔX₂, as seen in FIG. 3( b).During electroplating, the faster plating rate at the bottom 38facilitates the desirable void-free filling (or “superfilling”) profile,as shown in FIGS. 3( h) and 4(a).

The powerful jets agitation provides another important advantage. Itfacilitates significant increase of the plating rate without “burning”the deposit. It was found that the plating rate could be safelyincreased to 2.8 μm/min, without any deleterious effects. This is about8× faster than typical prior art plating rate of about 0.35 μm/min. Itfacilitates more than double the throughput per module, at no extracost. In fact, it was found that the surface becomes brighter byincreasing the plating rate. At 2.8 μm/min, wafers appear fully bright(cf. FIG. 4( b)). However, the surface brightness and roughness of theplated Cu layer is also a strong function of the seed layer. Some seedlayers result in significantly rougher plated Cu than others.

FIG. 5 shows an atomic force microscope (AFM) trace, taken over thesurface of a wafer which was Cu-plated using a conventional prior-arttool (Novellus Systems, Inc). The AFM trace was taken over a borderbetween flat field and an array of trenches of 0.35 m/0.35 μmlines/spaces. The wafer was plated to a nominal thickness of 1.5 μm. TheAFM trace shows a large spike (˜520 nm) and an elevation step (˜250 nm)at the border.

EXAMPLE 3

Using a JECD tool as in Example 2, two wafers were plated at low andhigh plating rates. All other plating parameters (or variables) wereidentical to those in Example 2. As in FIG. 5, the wafers had patternedarrays of 0.35/0.35 μm lines/spaces, and were plated to a nominalthickness of 1.5 μm. The first sample was plated at low current density(15 mA/cm² or ˜0.35 μm/min), and the second sample was plated at highcurrent density (120 mA/cm² or ˜2.8 μm/min). While the lower platingrate produced a small step (or hump) of about 140 nm at the field/arrayborder, the sample plated at the higher rate revealed no transitionspike or step at all. For comparison, FIG. 5 shows that a wafer platedby a prior art tool had a large spike (˜520 nm) and elevation step (˜250nm) at the border. Surface roughness of JECD plated samples was measuredby AFM. While the mean surface roughness (Ra) of a low current (15mA/cm²) sample was 11.2 nm, that of a sample plated at the highercurrent (120 mA/cm²) was only 7.3 nm.

JECD plating did not require any additional (third component) “leveler”organic additive, or the use of a complex pulse or periodic reversalpulse plating, in order to eliminate the spikes and steps common inprior art ECD plating. As disclosed in an article by Reid et al. inJournal of Solid State Technology, Vol. 43(7), pp. 86-103, July 2000,and in an article by Mikkola et al. in 2000 International InterconnectTechnology Conference (IITC), pp. 117-119, June 2000, addition of athird component “leveler” additive greatly complicates the required bathanalysis and control. It may also result in top center voids and poorfilling of larger features. As disclosed in an article by Gandikota etal. in 2000 International Interconnect Technology Conference (IITC), pp.239-241, June 2000, and in an article by Hsie et al. in 2000International Interconnect Technology Conference (IITC), pp. 182-184,June 2000, pulse plating, and in particular periodic reversal (PR)plating, slows-down the throughput and further complicates the requiredcontrol. It may also result in larger grains, rougher surface, andlonger self-anneal time of the plated Cu films.

FIG. 6 shows a schematic inhibition model explaining the improved JECDleveling and brightness with increasing plating rate. At low currentdensity (15 mA/cm²), there is only small depletion (ΔC₁₅) of theinhibitor at the wafer's interface. As a result, there is very little orno inhibition differentiation between a growing protrusion and the flatsurface. Due to higher concentration of the plating ions ahead of theflat interface, protrusions (after exceeding a critical size) cancontinue to grow faster than the flat surface. This leads toamplification of the protrusions and surface roughening. At high platingrate, the high current density (105 mA/cm²) creates larger (or deeper)depletion (ΔC₁₀₅

fsi ΔC₁₅) of the inhibitor at the (flat) wafer interface. The tip of agrowing protrusion “sees” significantly larger concentration of theinhibitor than the flat surface. Protrusions which stick into thediffusion layer are suppressed (or inhibited) by the higherconcentration of the inhibitor ahead of the flat surface. The flatsurface, on the other hand, “sees” deeper depletion (or lowerconcentration) of inhibitor as the current density increases, thusenhancing its deposition rate (relative to protrusions). As described inan article by Cohen et al. in 2000 Proc. 17^(th) Intl. VLSI MultilevelInterconnect Conference (VMIC), pp. 21-26, June 2000, and in the articleby Hsie et al., the enhanced suppression of protrusions at highercurrent densities leads to smoother and brighter deposits.

The common prior art humps or bumps are due to coalescence of individualmicro-bumps (above the top corners of openings) into larger bumps orhumps, associated with insufficient leveling or brightening. Thecoalesced bumps or humps continue to amplify and grow faster than theflat field, since they “see” larger concentration of the plating ionsahead of the flat field. The inventive methods improve leveling, therebyreducing or eliminating the bumps and humps. The most important factorfor leveling (for a given chemistry of additives and their bulkconcentrations) is to create a large concentration gradient across thediffusion layer (ΔC_(inh)/ΔX). In accordance with the invention, this isachieved by increasing the current density (larger ΔC_(inh)) and by thepowerful vigorous jets agitation (smaller ΔX).

As openings get narrower, the ratio of surface area (A) to volume (V) ofthe opening becomes larger. This ratio is reciprocal to W, the diameterof vias or width of trenches:

A/V∝1/W

A larger ratio A/V results in faster depletion of the inhibitor insidethe openings. In other words, it takes less time (keeping all otherparameters the same) to establish the inhibitor depletion gradientsinside the opening. This, in turn, results in thinner transitionalconformal growth on the bottom and sidewalls, prior to superfillcommencement. As described by the articles of Andricacos, and Andricacoset al., growing conformal and non-conformal (or anti-conformal) layerson the sidewalls lead to deleterious seam-voids in the center oftrenches or vias (cf. FIG. 1). Their thickness must be minimized inorder to achieve void-free filling. Thus, it is actually easier todeplete the inhibitor inside narrower openings! However, even completedepletion inside the openings does not guarantee void-free filling. Thelatter requires both, depletion of inhibitor inside the opening andsufficient supply of it at the top field. Without the latter, ΔC_(inh)between the field and the inside of the opening becomes too small toenable the superfill mechanism. This is where the inventive methodsbecome so beneficial. The powerful jets of JECD and/or brush wipingenhance considerably the supply of inhibitor to the field (compared withprior art tools and methods), thereby significantly increasing ΔC_(inh).The larger ΔC_(inh) produced by the inventive methods enablessuperfilling of even the narrowest (as well as the wider) openings, withwide process latitude.

EXAMPLE 4

FIG. 7 shows a scanning electron micrograph (SEM) of a cleaved sampleplated by a JECD tool, in accordance with the invention. The photo showsvoid-free filled trenches which were only about 0.05 μm wide (at theirbottom), about 1.41 μm deep, and had aspect ratio of about 28:1. Theplating current density was 30 mA/cm². All other plating parameters werethe same as in Examples 2 and 3. These are currently the narrowest (withlargest AR) void-free ECD Cu-filled trenches ever demonstrated.

FIG. 8 shows a preferred embodiment enhancing inhibitor supply to thefield, using a JECD apparatus similar to the one disclosed in U.S. Pat.No. 5,421,987. Anode segments 82 and jet nozzles 84 are assembled in amanner to provide high pressure jets producing uniform powerful andvigorous turbulent flow of electrolyte over the surface of a facingsubstrate (not shown). The nozzles 84 are assembled on a platen 86.Anode segments 82 may consist of a single copper sheet or a multiplicityof copper pieces electrically connected together. In order to improveaxial uniformity, either the anodes/jets assembly (AJA) rotates and thesubstrate is held stationary, or the substrate rotates and the AJA isheld stationary. Alternatively, both the AJA and the substrate rotate inopposite directions. The plating cell configuration may be horizontal orvertical. In the horizontal configuration the substrate (wafer) iseither facing down or is facing up the AJA. In the verticalconfiguration both the wafer and the AJA face each other in a verticalconfiguration. The powerful jets produce significantly enhanced supplyof inhibitor to the field, while maintaining substantially stagnantelectrolyte inside narrow openings.

FIG. 9 shows alternative embodiments in which enhanced inhibitor supplyto the field is produced by wiping brushes (or pads, or wiper blades)80. During electroplating, the brushes and/or the substrate move orrotate relative to, or across, each other in a manner to providemechanical wiping between the brushes (or pads, or wiper blades) and thesurface of the substrate (not shown). Although the description hereinrelates sometimes to brushes (or pads, or blades), it should beunderstood by those skilled in the art that the same description alsoapplies to a single brush (or a pad, or a wiper blade). The mechanicalwiping removes depleted electrolyte from the field surface, therebyenhancing replenishment of fresh (with undepleted inhibitor) electrolyteto the field. At the same time, electrolyte inside narrow openingsremains essentially stagnant and unremoved by the wiping brush (or pad,or wiper blade), thus leading to local depletion of inhibitor there. Thewiping pad (or blade, or brush) does not have to actually makecontinuous contact with the surface of the substrate. It is sufficientto move it (or to move the substrate relative to it) within closeproximity to the substrate's surface, in order to obliterate therelatively thick diffusion layer established prior to the wiping action.For example, a wiping blade (or pad or brush) within a distance of about5-50 μm from the substrate surface is sufficient to wipe out andobliterate the diffusion layer from the field and replenish it withfresh solution containing full inhibitor concentration. Non-contacting,or slightly contacting, wipe has the advantage of avoiding particulateformation due to rubbing between the wipe and the substrate's surface. Anon-contacting wipe can be obtained, for example, by hydrodynamicallyfloating the wipe over the substrate's surface, similar to floatingmagnetic heads over rotating disks, or by shaping the wipe to float asan hydrofoil or hydroplane.

In one embodiment, brushes (or pads, or blades) 80 alone, withoutjet-nozzles 84, produce significantly enhanced supply of inhibitor tothe field, while maintaining substantially stagnant electrolyte,containing depleted inhibitor, inside narrow openings. The relativewiping motion does not have to be rotational. It may also be linear (notshown).

In another embodiment, both high pressure jets (using jet-nozzles 84)and wiping brushes (or pads, or blades) 80 are combined together toproduce the benefits of both methods. They produce significantlyenhanced supply of inhibitor to the field, while maintainingsubstantially stagnant electrolyte (containing depleted inhibitor)inside narrow openings. The relative wiping motion does not have to berotational. It may also be linear (not shown).

In yet another embodiment, ultrasonic or megasonic agitation (notshown), with or without brushes 80 and/or jet-nozzles 84, producessignificantly enhanced supply of inhibitor to the field, whilemaintaining substantially stagnant electrolyte inside narrow openings.

The inventive methods increase the concentration gradients of theinhibitor, ΔCinh/h, along the depth (h) of the opening, thus producinglarger inhibition gradient from the field to the bottom of the opening.The larger this gradient, the more effective and prevalent the superfillmechanism. At large enough gradient, even the narrowest opening can befilled without voids. At the same time, increasing this gradient alsofacilitates wider process latitude. For example, utilizing a JECD tool,it was possible to obtain simultaneous void-free filling of very narrow,as well as wide openings, while using wide range of plating rates(0.35-2.8 μm/min). Similarly, using a JECD tool, it was possible to varythe nominal additive concentration by more than 100%, withoutdeleterious effects.

Other embodiments of the invention provide for one or more of thefollowing: (a) increasing the global plating rate (in order tofacilitate depletion of inhibitor inside openings); (b) narrowing theopenings and/or increasing their aspect ratio (in order to facilitatedepletion of inhibitor inside openings); (c) decreasing the bulkinhibitor concentration (in order to facilitate depletion of inhibitorinside openings); and (d) increasing adsorption strength (and inhibitioneffectiveness) by selecting at least one powerful inhibitor (oradsorbate).

However, it should be understood by those skilled in the art that thereare optimal ranges for these variables which may intricately depend oneach other. For example, while increasing the global plating ratefacilitates depletion of inhibitor inside the openings, it alsoincreases depletion of the inhibitor at the field. This may in turnrequire higher inhibitor bulk concentration. Therefore, the optimalrange of plating rate is strongly dependent upon inhibitorconcentration. Similarly, although depletion is faster inside narroweropenings (with larger AR), inherent void-forming effects (due to higherelectric field at the top corners and plating ion depletion inside theopenings) are stronger with such openings. Also, while decreasing bulkinhibitor concentration helps depletion inside the openings, it mayresult in insufficient concentration at the field, thereby adverselyaffecting void-free filling. Thus, too low or too high inhibitor bulkconcentration or global plating rate may result in insufficientinhibitor gradients for successful void-free filling. Too low inhibitorconcentration may result in insufficient field concentration, therebyproducing too small inhibitor gradients. Too high inhibitor bulkconcentration may result in insufficient depletion inside the openings,thereby leading to too small inhibitor gradients. Similarly, too lowplating rate may not be sufficient to deplete the inhibitor inside theopenings, while too high plating rate may deplete too much the field.Therefore, the optimal ranges of these variables are intricatelydependent on each other. They must be optimized in concert with eachother.

It should be understood that the above-described embodiments can be usedto fabricate any number of devices including, and without limitation,metallic interconnects in semiconductor integrated circuit devices, thinfilm heads, micromachined Microelectromechanical Systems (MEMS) devices,or interconnects in high density electronic packages (such as chip scaleand wafer scale packaging).

Those skilled in the art will recognize that the foregoing descriptionhas been presented for the sake of illustration and description only. Assuch, it is not intended to be exhaustive or to limit the invention tothe precise form disclosed.

What I claim is:
 1. A device comprising at least one filled via ortrench wherein: the at least one filled via or trench comprisesvoid-free filled metal or metal alloy; and the filled via or trench hasan aspect ratio in a range from 9:1 to about 28:1.
 2. The device ofclaim 1 wherein the void-free filled metal or metal alloy comprises amaterial selected from a group consisting of Cu, Ag, Cu alloys, and Agalloys.
 3. The device of claim 2 wherein the filled via or trench has awidth from about 0.05 μm to about 0.35 μm.
 4. The device of claim 2wherein the filled via or trench has a width from about 0.05 μm to 0.10μm.
 5. The device of claim 2 wherein: the filled via or trench issurrounded by one or more dielectric layers along its sidewalls; and oneor more barrier layers are interposed between the void-free filled metalor metal alloy and the one or more dielectric layers.
 6. The device ofclaim 5 further comprising a seed layer interposed between the void-freefilled metal or metal alloy and the one or more barrier layers; whereinthe void-free filled metal or metal alloy comprises copper or copperalloy.
 7. The device of claim 6 wherein the filled via or trench is afilled via.
 8. The device of claim 1 wherein the filled via or trenchhas an aspect ratio in a range from 10:1 to about 28:1.
 9. The device ofclaim 8 wherein the void-free filled metal or metal alloy comprises amaterial selected from a group consisting of Cu, Ag, Cu alloys, and Agalloys.
 10. The device of claim 9 wherein the filled via or trench has awidth from about 0.05 μm to about 0.35 μm.
 11. The device of claim 9wherein the filled via or trench has a width from about 0.05 μm to 0.10μm.
 12. The device of claim 9 wherein: the filled via or trench issurrounded by one or more dielectric layers along its sidewalls; and oneor more barrier layers are interposed between the void-free filled metalor metal alloy and the one or more dielectric layers.
 13. The device ofclaim 12 further comprising a seed layer interposed between thevoid-free filled metal or metal alloy and the one or more barrierlayers; wherein the void-free filled metal or metal alloy comprisescopper or copper alloy.
 14. The device of claim 13 wherein the filledvia or trench is a filled via.
 15. The device of claim 1 wherein thefilled via or trench has an aspect ratio in a range from 12:1 to about28:1.
 16. The device of claim 15 wherein the void-free filled metal ormetal alloy comprises a material selected from a group consisting of Cu,Ag, Cu alloys, and Ag alloys.
 17. The device of claim 16 wherein thefilled via or trench has a width from about 0.05 μm to about 0.35 μm.18. The device of claim 16 wherein the filled via or trench has a widthfrom about 0.05 μm to 0.10 μm.
 19. The device of claim 16 wherein: thefilled via or trench is surrounded by one or more dielectric layersalong its sidewalls; and one or more barrier layers are interposedbetween the void-free filled metal or metal alloy and the one or moredielectric layers.
 20. The device of claim 19 further comprising a seedlayer interposed between the void-free filled metal or metal alloy andthe one or more barrier layers; and the void-free filled metal or alloycomprises copper or copper alloy.
 21. The device of claim 20 wherein thefilled via or trench is a filled via.
 22. The device of claim 1 whereinthe filled via or trench has an aspect ratio in a range from 14:1 toabout 28:1.
 23. The device of claim 22 wherein the void-free filledmetal or metal alloy comprises a material selected from a groupconsisting of Cu, Ag, Cu alloys, and Ag alloys.
 24. The device of claim23 wherein the filled via or trench has a width from about 0.05 μm toabout 0.35 μm.
 25. The device of claim 23 wherein the filled via ortrench has a width from about 0.05 μm to 0.10 μm.
 26. The device ofclaim 23 wherein: the filled via or trench is surrounded by one or moredielectric layers along its sidewalls; and one or more barrier layersare interposed between the void-free filled metal or metal alloy and theone or more dielectric layers.
 27. The device of claim 26 furthercomprising a seed layer interposed between the void-free filled metal ormetal alloy and the one or more barrier layers; and the void-free filledmetal or alloy comprises copper or copper alloy.
 28. The device of claim27 wherein the filled via or trench is a filled via.
 29. The device ofclaim 1 wherein the filled via or trench is a filled via.
 30. The deviceof claim 8 wherein the filled via or trench is a filled via.
 31. Thedevice of claim 15 wherein the filled via or trench is a filled via. 32.The device of claim 22 wherein the filled via or trench is a filled via.